The present invention is related to logic delay testing, in particular in the context of logic circuit designs.
Ascertaining the correct operation of digital logic circuits requires verification of functional behavior as well as correct operation at desired clock rates. Failures that cause logic to malfunction at desired clock rates are referred to as delay faults. These delay faults, particularly those occurring within integrated circuits, are typically due to random variations in process parameters that may cause device and/or wiring propagation delays to exceed specified limits. The detection of a delay fault normally requires application of a two-pattern test: a first pattern that initializes the targeted faulty circuit line to a desired value and a second pattern that launches a transition at the circuit line and propagates the fault effect to one or more primary outputs or scan flip-flops. In the “skewed-load” or “launch-by-shift” approach, the second pattern is obtained by a one bit shift of the first pattern, i.e., by shifting the first pattern by one more scan flip-flop. Hence, given a first pattern, there are only two possible patterns for the second pattern that differs only at the value for the first scan flip-flop whose scan input is connected to the scan chain input. Due to this dependency of second patterns on first patterns, transition delay fault coverage in a standard scan environment is sometimes significantly lower than stuck-at-fault coverage. If a pair of adjacent flip-flops drive the same fanout cone, then the correlation between the pair may create untestable delay faults.
There are a variety of techniques for increasing the delay fault coverage in a standard scan environment. For example, all or some of the standard scan cells can be replaced by enhanced scan cells which can hold two bits. See B. Dervisoglu and G. Stong, “Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement,” in Proc. International Test Conference, pp. 365–74 (1991); K.-T. Cheng, S. Devadas, and K. Keutzer, “A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits,” in Proc. International Test Conference, pp. 403–10 (1991). If a pair of adjacent scan flip-flops are correlated (drive the same fanout cone), a combinational gate or flip-flop can be inserted between the flip-flops to break the shift dependency. See S. Patil and J. Savir, “Skewed-Load Transition Test: Part II, Coverage,” in Proc. International Test Conference, pp. 714–22 (1992); S. Wang and S. T. Cahkradhar, “A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs,” in Proc. International Test Conference, pp. 574–83 (2003). See also U.S. patent application Ser. No. 10/736,879, filed on Dec. 16, 2003, the contents of which are incorporated by reference herein.
A less intrusive way to enhance delay fault coverage is to rearrange the scan flip-flops to minimize the number of pairs of adjacent scan flip-flops that are correlated with each other (scan flip-flops that drive the same fanout cones). Scan flip-flops can be relocated to new locations in the scan chain so as to enhance delay fault coverage. In W. W. Mao and M. D. Ciletti, “Reducing Correlation to Improve Coverage of Delay Faults in Scan-Path Design,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and System, pp. 638–46 (1994), the circuit's topology is used to find a scan order that minimizes the number of adjacent scan flip-flop pairs that drive the same fanout cones. However, it turns out that even if a pair of adjacent flip-flops drive the same fanout cone, it may not cause any shift dependency untestable faults. In J. Savir and R. Berry, “At-Speed Test is not Necessarily an AC Test,” in Proc. International Test Conference, pp. 722–28 (1991), a circuit function rather than a simple topology is used to find a best scan order. A fault simulation is run with a set of random patterns for a large number of randomly generated scan orders. The number of untestable faults for each scan order is counted and the scan order that achieves the highest fault coverage is selected. This, unfortunately, requires prohibitive CPU time and is not practical for large circuits that have a million or more gates.
Accordingly, there is a need for a more practical methodology for enhancing delay fault coverage that can be achieved with a reasonable resources even for large circuits.